module opcdec
	(
	 DATA,
	 branch, decabnz, decbbnz,
	 ioset, loada, loadb,
	 swait, waitint,
	 ramp, rsram, rlta,
	 initperi
	);
input	[3:0]	DATA;
output			branch, decabnz, decbbnz;
output			ioset, loada, loadb;
output			swait, waitint;
output			ramp, rsram, rlta;
output			initperi;

reg				branch, decabnz, decbbnz;
reg				ioset, loada, loadb;
reg				swait, waitint;
reg				ramp, rsram, rlta;
reg				initperi;

parameter	BRANCH=4'h2, DECABNZ=4'h3, DECBBNZ=4'h1,
			IOSET=4'h4, LOADA=4'h5, LOADB=4'h7,
			SWAIT=4'h6, WAITINT=4'h9,
			RAMP=4'h8, RSRAM=4'ha, RLTA=4'hc,
			INITPERI=4'hB;

always @(DATA)
begin
	case (DATA)
		BRANCH:
		begin
			branch   <= 1;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		DECABNZ:
		begin
			branch   <= 0;  decabnz <= 1; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		DECBBNZ:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 1;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		IOSET:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 1;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		LOADA:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 1; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		LOADB:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 1;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		SWAIT:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 1;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		WAITINT:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 1;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end

		RAMP:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 1;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
		RSRAM:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 1; rlta    <= 0;
			initperi <= 0;
		end
		RLTA:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 1;
			initperi <= 0;
		end
		INITPERI:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 1;
		end

		default:
		begin
			branch   <= 0;  decabnz <= 0; decbbnz <= 0;
			ioset    <= 0;  loada   <= 0; loadb   <= 0;
			swait    <= 0;  waitint <= 0;
			ramp     <= 0;  rsram   <= 0; rlta    <= 0;
			initperi <= 0;
		end
	endcase
end

endmodule